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high voltage latch - up proof, 4 - /8 - channel multiplexers data sheet adg5408 / a dg 5409 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks a nd registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2012 analog devices, inc. all rights reserved. features latch - up proof 8 kv h uman body model (h bm ) esd rating low on resistance ( 1 3. 5 ?) 9 v to 2 2 v dual - supply operation 9 v to 40 v single - supply operation 48 v supply maximum ratings fully s pecified at 15 v , 20 v , +12 v , and +36 v v ss to v dd ana log signal range applications relay replacement automatic test equipment d ata acquisition instrumentation avionics audio and video switching communication systems functional block dia gram s adg5408 s1 s8 d adg5409 s1a s4b da db s4a s1b 1-of-4 decoder 1-of-8 decoder a0 a1 en a0 a1 a2 en 09206-001 figure 1. general description the adg 5 408/adg 5 409 are mo nolithic cmos analog multi - p lexers comprising eight single channels and four differential channels, respectively. the adg 5 408 switches one of eight inputs to a co mmon output, as determined by the 3 - bit binary address lines, a0, a1, and a2 . the adg 5 409 switches one of four differential inputs to a common differential output, as determined by the 2 - bit binary address lines, a0 and a1. an en input on both devices enable s or disable s the device. when en is disabled, all channels switch off . t he on - resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. high switching speed also makes the parts suitable for video signal switching. each switch conducts equal ly well in both directions when on , and each switch has an input signal range that extends to the power supplies. in the off condition, signal levels up to the supplies are blocked. the adg 5408/adg5409 do not have v l pin s; rather, the logic power supply is generated internally by an on - chip voltage generator . product highlights 1. trenc h isolation guards against latch - up. a dielectric trench separates the p and n channel transistors thereby preventing latch - up even under severe overvoltage conditions. 2. low r o n . 3. dual - supply operation . for applications where the analog signal is bi polar, the adg 5 4 08/adg5409 can be operated from dual supplies up to 2 2 v . 4. single - supply operation . for applications where the analog sign al is unipolar, the adg5408/adg5409 can be op erated from a single rail power supply up to 40 v . 5. 3 v logic compatible digital inputs: v i n h = 2.0 v, v i n l = 0.8 v. 6. no v l logic power supply required .
adg5408/adg5409 data sheet rev. b | p age 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ........................................................................... 2 specifications ..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply ........................................................................ 5 36 v single supply ........................................................................ 6 continuous current per channel, sx or d ............................... 8 absolute maximum ratings ............................................................9 esd caution ...................................................................................9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 12 test circuits ..................................................................................... 16 terminology .................................................................................... 18 trench isolation .............................................................................. 19 applications information .............................................................. 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 22 revision history 5 / 12 rev . a to rev. b removed automotive information (throughout) ....................... 1 changes to ordering guide .......................................................... 22 deleted automotive products section ......................................... 22 6 / 11 rev . 0 to rev. a change to fea tures section ............................................................. 1 change to i ss parameter, table 2 ..................................................... 5 changes to figure 3 ........................................................................ 10 changes to figure 5 ........................................................................ 11 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 added automotive products section ........................................... 21 7/ 10 rev ision 0: initial version
data sheet adg5408/adg5409 rev. b | page 3 of 24 specifications 15 v dual supp ly v dd = + 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 13.5 ? typ v s = 10 v, i s = ?10 ma; see figure 26 15 18 22 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels, ? r on 0.3 ? typ v s = 10 v , i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness , r flat (on) 1.8 ? typ v s = 10 v, i s = ?10 ma 2 .2 2.6 3 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.05 na typ v s = 10 v, v d = ? 1 0 v; see figure 29 0.25 1 7 na max drain off leakage, i d (off ) 0.1 na typ v s = 10 v, v d = ? 10 v; see figure 29 0.4 4 30 na max channel on leakage, i d (on), i s (on) 0.1 n a typ v s = v d = 10 v; see figure 25 0.4 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 170 ns typ r l = 300 ?, c l = 35 pf 217 258 292 ns max v s = 10 v ; see figure 32 t on (en) 1 40 ns typ r l = 300 ?, c l = 35 pf 175 213 242 ns max v s = 10 v; see figure 34 t off (en) 130 ns typ r l = 300 ?, c l = 35 pf 161 183 198 ns max v s = 10 v; see fig ure 34 break - before - make time delay, t d 50 ns typ r l = 300 ?, c l = 35 pf 16 ns min v s1 = v s2 = 10 v; see figure 33 charge injection, q inj 115 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figu re 35 off isolation ?60 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 28 channel - to - channel crosstalk ?60 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.01 % typ r l = 1 k? , 15 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth r l = 50 ?, c l = 5 pf; see figure 31 adg5408 50 mhz typ adg5409 87 mhz typ insertion loss 0.9 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; figure 31 c s (off ) 15 pf typ v s = 0 v, f = 1 mhz c d (off ) adg5408 102 pf typ v s = 0 v, f = 1 mhz adg5409 50 pf typ v s = 0 v, f = 1 mhz
adg5408/adg5409 data sheet rev. b | p age 4 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments c d (on), c s (on) adg5408 133 pf typ v s = 0 v, f = 1 mhz adg5409 81 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9 /22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 20 v dual supply v dd = + 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 12.5 ? typ v s = 15 v, i s = ?10 ma; see figure 26 14 17 21 ? max v dd = +18 v, v ss = ?18 v on - resistance match between channels, ? r on 0 .3 ? typ v s = 15 v , i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 2.3 ? typ v s = 15 v, i s = ?10 ma 2.7 3.1 3.5 ? max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0. 1 na typ v s = 15 v, v d = ? 15 v; see figure 29 0.25 1 7 na max drain off leakage, i d (off ) 0. 1 5 na typ v s = 15 v, v d = ? 15 v; see f igure 29 0. 4 4 30 na max channel on leakage, i d (on), i s (on) 0.1 5 na typ v s = v d = 15 v; see figure 25 0.4 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 160 ns typ r l = 300 ?, c l = 35 pf 2 07 237 262 ns max v s = 10 v ; see figure 32 t on (en) 140 ns typ r l = 300 ?, c l = 35 pf 165 194 218 ns max v s = 10 v; see figure 34 t off (en) 133 ns typ r l = 300 ?, c l = 35 pf 153 174 189 ns max v s = 10 v; see figure 34 break - before - make time delay, t d 38 ns typ r l = 300 ?, c l = 35 pf 11 ns min v s1 = v s2 = 10 v; see figure 33 charge injection, q inj 155 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 35 off isolation ?60 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 28 channel - to - channel crosstalk ?60 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27
data sheet adg5408/adg5409 rev. b | page 5 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments total harmonic distortion + noise 0.012 % typ r l = 1 k? , 20 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth r l = 50 ?, c l = 5 pf; see figure 31 adg5408 50 mhz typ adg5409 88 mhz typ insertion loss 0.8 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 c s (off ) 17 pf typ v s = 0 v, f = 1 mhz c d (off ) adg5408 98 pf t yp v s = 0 v, f = 1 mhz adg5409 48 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) adg5408 128 pf typ v s = 0 v, f = 1 mhz adg5409 80 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inpu ts = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9 /22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 26 ? typ v s = 0 v to 10 v, i s = ?10 ma; see figure 26 30 36 42 ? max v dd = 10.8 v, v ss = 0 v on - resistance match between channels, ? r on 0.3 ? typ v s = 0 v to 10 v, i s = ?10 ma 1 1.5 1.6 ? max on - resistance flatness, r flat (on) 5.5 ? typ v s = 0 v to 10 v, i s = ?10 ma 6.5 8 12 ? max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.0 2 na typ v s = 1 v/10 v, v d = 10 v/ 1 v; see figure 29 0.25 1 7 na max drain off leakage, i d (off ) 0. 05 na typ v s = 1 v/10 v, v d = 10 v/ 1 v; see figure 29 0. 4 4 30 na max channel on leakage, i d (on), i s (on) 0. 05 na typ v s = v d = 1 v/10 v; see figure 25 0.4 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ
adg5408/adg5409 data sheet rev. b | p age 6 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments dynamic characteristics 1 transition time, t tran sition 230 ns typ r l = 300 ?, c l = 35 pf 321 388 430 ns max v s = 8 v ; see figure 32 t on (en) 215 ns typ r l = 300 ? , c l = 35 pf 276 345 397 ns max v s = 8 v; see figure 34 t off (en) 134 ns typ r l = 300 ? , c l = 35 pf 161 187 209 ns max v s = 8 v; see figure 34 break - before - make time delay, t d 118 ns typ r l = 300 ? , c l = 35 pf 55 ns min v s1 = v s2 = 8 v; see figure 33 c harge injection, q inj 45 pc typ v s = 6 v, r s = 0 ? , c l = 1 nf; see figure 35 off isolation ?60 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 28 channel - to - channel crosstalk ?60 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.1 % typ r l = 1 k? , 6 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth r l = 50 ?, c l = 5 pf; see figure 31 adg5408 35 mhz typ adg5409 74 mhz typ insertion loss ?1.8 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 c s (off ) 22 pf typ v s = 6 v, f = 1 mhz c d (off ) adg5408 119 pf typ v s = 6 v, f = 1 mhz adg5409 59 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) adg5408 146 pf typ v s = 6 v, f = 1 mhz adg5409 86 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v o r v dd 50 65 a max v dd 9 /40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 14.5 ? typ v s = 0 v to 30 v, i s = ?10 ma; see figure 26 16 19 23 ? max v dd = 32.4 v, v ss = 0 v on - resistance match between channels, ? r on 0.3 ? typ v s = 0 v to 30 v, i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 3.5 ? typ v s = 0 v to 30 v, i s = ?10 ma 4.3 5.5 6.5 ? max leakage currents v dd =39.6 v, v ss = 0 v source off leakage, i s (off ) 0. 1 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 29 0.25 1 7 na max
data sheet adg5408/adg5409 rev. b | page 7 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments drain off leakage, i d (off ) 0. 1 5 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 29 0. 4 4 30 na max channel on leakage, i d (on), i s (on) 0.1 5 na typ v s = v d = 1 v/30 v; see figure 25 0.4 4 30 na max digital inputs i nput high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 187 ns typ r l = 300 ?, c l = 35 pf 242 257 281 ns max v s = 1 8 v ; see figure 32 t on (en) 160 ns typ r l = 300 ? , c l = 35 pf 195 219 237 ns max v s = 18 v; see figure 34 t off (en) 147 ns typ r l = 300 ? , c l = 3 5 pf 184 184 190 ns max v s = 18 v; see figure 34 break - before - make time delay, t d 53 ns typ r l = 300 ? , c l = 35 pf 17 ns min v s1 = v s2 = 18 v; see figure 33 charge injection, q inj 150 p c typ v s = 18 v, r s = 0 ? , c l = 1 nf; see figure 35 off isolation ?60 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 28 channel - to - channel crosstalk ?60 db typ r l = 50 ? , c l = 5 pf, f = 1 mh z; see figure 27 total harmonic distortion + noise 0.4 % typ r l = 1 k? , 18 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth r l = 50 ?, c l = 5 pf; see figure 31 adg5408 45 mhz typ adg5409 76 mhz typ insertion loss ? 1 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 c s (off ) 18 pf typ v s = 18 v, f = 1 mhz c d (off ) adg5408 120 pf typ v s = 18 v, f = 1 mhz adg5409 60 pf typ v s = 18 v, f = 1 mhz c d (on) , c s (on) adg5408 137 pf typ v s = 18 v, f = 1 mhz adg5409 80 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9 /40 v min/v max gnd = 0 v, v ss = 0 v 1 guarante ed by design; not subject to production test.
adg5408/adg5409 data sheet rev. b | p age 8 of 24 continuous current p er channel , s x or d table 5 . adg5408 parameter 25c 85c 125c unit continuous current, s x or d v dd = + 1 5 v, v ss = ?1 5 v tssop ( ja = 1 12.6 c/w) 100 44 16 ma maximum lfcsp ( ja = 30.4 c/w) 170 54 16 ma maximum v dd = + 20 v, v ss = ?20 v tssop ( ja = 1 12.6 c/w) 106 45 16 ma maximum lfcsp ( ja = 30.4 c/w) 178 55 16 ma maximum v dd = 12 v, v ss = 0 v tss op ( ja = 1 12.6 c/w) 81 39 15 ma maximum lfcsp ( ja = 30.4 c/w) 140 51 16 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 1 12.6 c/w) 104 44 16 ma maximum lfcsp ( ja = 30.4 c/w) 175 55 16 ma maximum table 6 . adg5409 parameter 25c 85c 125c unit continuous current, s x or d v dd = + 1 5 v, v ss = ?1 5 v tssop ( ja = 1 12.6 c/w) 75 37 15 ma maximum lfcsp ( ja = 30.4 c/w) 130 49 16 ma maximum v dd = + 20 v, v ss = ?20 v tssop ( ja = 1 12.6 c/w) 79 38 15 ma maximum lfcsp ( ja = 30.4 c/w) 136 50 16 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 1 12.6 c/w) 60 32 14 ma maximum lfcsp ( ja = 30.4 c/w) 105 44 16 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 1 12.6 c/w) 78 38 15 ma maximum lfcsp ( ja = 30.4 c/w) 133 5 0 16 ma maximum
data sheet adg5408/adg5409 rev. b | page 9 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 7 . parameter rating v dd to v ss 4 8 v v dd to gnd ?0.3 v to +4 8 v v ss to gnd +0.3 v to ?4 8 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 m a, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or d pins adg5408 370 ma (pulsed at 1 ms, 10% duty cycle maximum) adg5409 275 ma (pulsed at 1 ms, 10% duty cycle maximum) continuou s current , sx or d 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance, ja 16- lead tssop (4 - layer board) 1 12.6 c/w 16- lead lfcsp (4 - layer board) 30.4 c/w reflow soldering peak temperature, pb free 260(+0/?5)c 1 overvoltages at the a x , en, s x, and d pins are clamped by internal diodes. limit c urrent to the maximum ratings given. 2 see table 5 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exp osure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution
adg5408/adg5409 data sheet rev. b | p age 10 of 24 pin configurations a nd function descript ions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 en v ss s1 s4 s3 s2 a0 a2 gnd v dd s7 d s8 s6 s5 a1 adg5408 top view (not to scale) 09206-002 figure 2 . adg 5 408 pin configuration (tssop) 1 v ss notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 2 s1 3 s2 4 s3 1 1 v dd 12 gnd 10 s5 9 s6 5 s4 6 d 7 s8 8 s7 15 a0 16 en 14 a1 13 a2 09206-003 top view (not to scale) adg5408 figure 3 . adg 5 408 pin configuration (lfcsp) table 8 . adg 5 408 pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single - supply applications, this pin c an be connected to ground. 4 2 s1 source terminal 1. this pin c an be an input or an output. 5 3 s2 source terminal 2. this pin c an be an input or an output. 6 4 s3 source terminal 3. this pin c an be an input or an output. 7 5 s4 source terminal 4. this pin c an be an input or an output. 8 6 d drain terminal. this pin c an be an input or an output. 9 7 s8 source terminal 8. this pin c an be an input or an output. 10 8 s7 source terminal 7. this pin c an be an input or an output. 11 9 s6 source terminal 6. this pin c an be an input or an output. 12 10 s5 source terminal 5. this pin c an be an input or an output. 13 11 v dd most positive power supply potential. 14 12 gnd ground (0 v) reference. 15 13 a2 logic control input. 16 14 a1 logic control input. ep exposed pa d the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . table 9 . adg 5 408 truth table a2 a1 a0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8
data sheet adg5408/adg5409 rev. b | page 11 of 24 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 en v ss s1a s4a s3a s2a a0 gnd v dd s1b s4b da db s3b s2b a1 adg5409 top view (not to scale) 09206-004 figure 4 . adg 5 409 pin configuration (tssop) 1 v ss 2 s1a 3 s2a 4 s3a 11 s1b 12 v dd 10 s2b 9 s3b 5 s4a 6 da 7 db 8 s4b 15 a0 16 en 14 a1 13 gnd notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 09206-005 top view (not to scale) adg5409 figure 5 . adg 5 409 pin configuration (lfcsp) table 10 . adg5 409 pin function descriptions pin no. tssop lfcsp nemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single - supply applications, this pin c an be connected to ground. 4 2 s1a source terminal 1a. this pin c an be an inp ut or an output. 5 3 s2a source terminal 2a. this pin c an be an input or an output. 6 4 s3a source terminal 3a. this pin c an be an input or an output. 7 5 s4a source terminal 4a. this pin c an be an input or an output. 8 6 da drain terminal a. this pin c an be an input or an output. 9 7 db drain terminal b. this pin c an be an input or an output. 10 8 s4b source terminal 4b. this pin c an be an input or an output. 11 9 s3b source terminal 3b. this pin c an be an input or an output. 12 10 s2b source termi nal 2b. this pin c an be an input or an output. 13 11 s1b source terminal 1b. this pin c an be an input or an output. 14 12 v dd most positive power supply potential. 15 13 gnd ground (0 v) reference. 16 14 a1 logic control input. ep exposed pad the ex posed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . table 11 . adg5 409 truth table a1 a0 en on switch pair x x 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4
adg5408/adg5409 data sheet rev. b | p age 12 of 24 typical performance characteristics 0 5 10 15 20 25 ?18 ?14 ?10 ?6 ?2 2 6 10 14 18 on resis t ance () v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +10v v ss = ?10v v dd = +11v v ss = ?11v v dd = +13.5v v ss = ?13.5v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 09206-028 figure 6. r on as a function of v s , v d ( dual supply ) 0 2 4 6 8 10 12 14 16 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resis t ance () v s , v d (v) t a = 25c v dd = +22v v ss = ?22v v dd = +20v v ss = ?20v v dd = +18v v ss = ?18v 09206-029 figure 7. r on as a function of v s , v d ( dual supply ) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 on resis t ance () v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10v v ss = 0v v dd = 10.8v v ss = 0v v dd = 11v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 09206-023 figure 8. r on as a function of v s , v d (single supply ) 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 40 45 on resis t ance () v s , v d (v) t a = 25c v dd = 39.6v v ss = 0v v dd = 36v v ss = 0v v dd = 32.4v v ss = 0v 09206-027 figure 9. r on as a function of v s , v d (single supply ) 0 5 10 15 20 25 ?15 ?10 ?5 0 5 10 15 on resis t ance () v s , v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 09206-030 figure 10 . r on as a function of v s (v d ) f or different temperatures , 15 v dual supply 0 5 10 15 20 25 ?20 ?15 ?10 ?5 0 5 10 15 20 on resis t ance () t a = +125c t a = +85c t a = +25c t a = ?40c v s , v d (v) v dd = +20v v ss = ?20v 09206-024 figure 11 . r on as a function of v s (v d ) for different temperatures , 20 v dual supply
data sheet adg5408/adg5409 rev. b | page 13 of 24 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 v s , v d (v) on resis t ance () t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v 09206-031 figure 12 . r on as a function of v s (v d ) for different temperature s, 12 v single supply 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 on resis t ance () t a = +125c t a = +85c t a = +25c t a = ?40c v s , v d (v) v dd = 36v v ss = 0v 09206-032 figure 13 . r on as a function of v d (v s ) for different temperatures , 36 v single supply 0 25 50 75 100 125 leakage current (na) temper a ture (c) 0.5 ?1.0 0 ?2.0 ?0.5 ?1.5 v dd = +15v v ss = ?15v v bias = +10v/?10v i d , i s (on) + + i d , i s (on) ? ? i d (off) + ? i s (off) + ? i s (off) ? + i d (off) ? + 09206-034 figure 14 . leakage currents vs. temperature, 15 v dual supply 0 25 50 75 100 125 leakage current (na) temper a ture (c) 1 ?1 0 ?3 ?2 v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i d , i s (on) ? ? i d (off) + ? i s (off) + ? i s (off) ? + i d (off) ? + 09206-035 figure 15 . leakage currents vs. temperature, 20 v dual supply 0 25 50 75 100 125 leakage current (na) temper a ture (c) 0.5 ?1.0 0 ?2.0 ?0.5 ?1.5 v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) + + i d , i s (on) ? ? i d (off) + ? i s (off) + ? i d (off) ? + i s (off) ? + 09206-033 figure 16 . leakage currents vs. temperature, 12 v single supply 0 25 50 75 100 125 leakage current (na) temper a ture (c) 1 ?1 0 ?3 ?2 v dd = +36v v ss = 0v v bias = 1v/30v i d , i s (on) + + i d , i s (on) ? ? i d (off) + ? i s (off) + ? i s (off) ? + i d (off) ? + 09206-036 figure 17 . leakage currents vs. temperature, 36 v single supply
adg5408/adg5409 data sheet rev. b | p age 14 of 24 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 off isol a tion (db) frequenc y (hz) 100k 10k 1m 10m 100m 1g 1k t a = 25c v dd = +15v v ss = ?15v 09206-021 figure 18 . off isolation vs. frequency , 15 v dual supply ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 cross t alk (db) frequenc y (hz) 10k 100k 1m 10m 100m 1g t a = 25c v dd = +15v v ss = ?15v 09206-026 figure 19 . crosstalk vs. frequency, 15 v dual supply 0 50 100 150 200 250 300 20 10 0 10 20 30 40 charge injection (pc) t a = 25c v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v v s (v) 09206-019 figure 20 . charge injection vs. source voltage ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) frequenc y (hz) 1k 1m 10m 10k 100k t a = 25c v dd = +15v v ss = ?15v no decoupling capacitors decoupling capacitors 09206-022 figure 21 . acpsrr vs. frequency , 15 v dual supply 0 0.02 0.04 0.06 0.08 0.10 0.12 0 5 10 15 20 thd + n (%) frequenc y (khz) v dd = 12v, v ss = 0v, v s = 6v p-p v dd = 36v, v ss = 0v, v s = 18v p-p v dd = 15v, v ss = 15v, v s = 15v p-p v dd = 20v, v ss = 20v, v s = 20v p-p load = 1k t a = 25c 09206-025 figure 22 . thd + n vs. frequency ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 insertion loss (db) frequenc y (hz) 10k 100k 1m 10m 100m 1k 1g adg5408 adg5409 t a = 25c v dd = +15v v ss = ?15v 09206-020 figure 23 . bandwidth
data sheet adg5408/adg5409 rev. b | page 15 of 24 0 50 100 150 200 250 300 350 400 ?40 ?20 0 20 40 60 80 100 120 time (ns) v dd = +12v, v ss = 0v v dd = +15v, v ss = ?15v v dd = +36v, v ss = 0v v dd = +20v, v ss = ?20v temper a ture (c) 09206-018 figure 24 . t transition times vs. temperature
adg5408/adg5409 data sheet rev. b | page 16 of 24 test circuits 09206-008 sx dx a v d i d (on) nc nc = no connect figure 25. on leakage sx d v s v1 i ds r on = v 1 /i ds 09206-006 figure 26. on resistance channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r l 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 09206-014 figure 27. channel-to-channel crosstalk v out 50 ? network analyzer r l 50 ? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50 ? off isolation = 20 log v out v s 09206-013 figure 28. off isolation v s v d sx d a a i s (off) i d (off) 09206-007 figure 29. off leakage v out r s audio precision r l 10k ? in v in sx d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 09206-015 figure 30. thd + noise figure v out 50? network analyzer r l 50 ? sx d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 09206-017 figure 31. bandwidth
data sheet adg5408/adg5409 rev. b | page 17 of 24 3v 0v output t r < 20ns t f < 20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output adg5408* a0 a1 a2 50? 300? gnd s1 s2 to s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s1 v s8 * similar connection for adg5409. 09206-009 figure 32 . address to output switching times, t transition output adg5408* a0 a1 a2 50? 300? gnd s1 s2 to s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s * similar connection for adg5409. 3v 0v output 80% 80% address drive (v in ) t d 09206-010 figure 33 . break - before - make delay, t d output adg5408* a0 a1 a2 50? 300? gnd s1 s2 to s8 d 35pf v in en v dd v ss v dd v ss v s *similar connection for adg5409. 3v 0v output 50% 50% t off (en) t on (en) 0.9v o 0.9v o enable drive (v in ) 09206-0 1 1 figure 34 . enable delay, t on (en), t off (en) 3v v in v out q inj = c l v out v out d sx en gnd c l 1nf v out v in r s v s v dd v ss v dd v ss a0 a1 a2 adg5408* *similar connection for adg5409. 09206-012 figure 35 . charge injection
adg5408/adg5409 data sheet rev. b | p age 18 of 24 terminology i dd i dd represents the p ositive supply current. i ss i ss re presents the n egative supply current. v d , v s v d and v s represent t he analog voltage on terminal d and terminal s , respectively . r on r on is the ohmic resistance between terminal d and terminal s. ? r on ? r on represents the difference between the r on of any two channels . r flat (on) the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by r flat (on) . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in represents digital input capacitance. t on ( en ) t on ( en) represen ts the delay time between the 50% and 90% points of the digital input and switch on condition. t off ( en ) t off ( en ) represents the delay time between the 50% and 90% points of the digital input and switch off condition. t trans ition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t d t d represents the off time measured between the 80% point of both switches when switching from one address state to another. off iso lation off isolation is a measure of unwanted signal coupling through an off channel. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is t he frequency at which the output is attenuated by 3 db. on response on response is t he frequency response of the on switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by thd + n . ac power supply rejection ratio (acpsrr) acpsrr is a measure of the ability of a part to avoid c oupling noise and spurious signals that ap pear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p - p. the ratio of the amplitude of signal on the output to the amplitude of the modulat ion is the acpsr r.
data sheet adg5408/adg5409 rev. b | page 19 of 24 trench isolation in the adg 5408/adg5409 , an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switch es, are eliminated, and the result is a completely latch - up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under normal operation. however, during overvoltag e conditions, this dio de can become forward - biased. a silicon controlled rectifier (scr) type circuit is formed by the two transistors causing a significant amplification of the current that , in turn , leads to latch - up. with trench isolation, this diode is removed, and the resu lt is a latch - up proof switch. 09206-016 nmos pmos p- w e l l n - w e l l buried oxide layer handle wafer t r e n c h figure 36 . trench isolation
adg5408/adg5409 data sheet rev. b | p age 20 of 24 applications informa tion the adg54xx family switches and multiplexers provide a robust solution for instrumentation, i ndustrial , aerospace , and other harsh environme nts that are prone to latch - up, which is an undesirable high current state that can lead to device failure and persist until t he power supply is turned off. the adg5408/ adg5409 high voltage switches allow single - supply operation from 9 v to 40 v and dual - supply operation from 9 v to 22 v. the adg5408/ adg54 09 (as well as select devices within the same family ) achieve a n 8 kv human body model esd rating that provides a robust solution eliminating the need for separate protect circuitry designs in some appl ications.
data sheet adg5408/adg5409 rev. b | page 21 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 37 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant t o jedec standards mo-220-wggc. 1 0.65 bsc b o t t o m v i e w t o p v i e w 1 6 5 8 9 1 2 1 3 4 e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indica t or 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16- 2010-c figure 38 . 16 - lead lead frame chip scale package [lfcsp_ w q] 4 mm 4 mm body, very very thin quad (cp - 16 - 17 ) dimensions shown in millimeters
adg5408/adg5409 data sheet rev. b | p age 22 of 24 ordering guide model 1 temperature range package description package option adg5408 b ruz ? 40c to +125c 1 6 - lead thi n shrink small outline package [ tssop ] ru -1 6 adg5408 b ruz - reel7 ? 40c to +125c 1 6 - lead thin shrink small outline package [ tssop ] ru -1 6 adg5408 b cpz - reel7 ? 40c to +125c 16- lead lead frame chip scale package [ lfcsp_ w q ] cp -16-1 7 adg5409 b ruz ? 40c to +125c 1 6 - lead thin shrink small outline package [ tssop ] ru -1 6 ad g5409b ruz - reel7 ? 40c to +125c 1 6 - lead thin shrink small outline package [ tssop ] ru -1 6 adg5409 b cpz - reel7 ? 40c to +125c 16- lead lead frame chip scale package [ lfcsp_ w q ] cp -16-1 7 1 z = rohs compliant part.
data sheet adg5408/adg5409 rev. b | page 23 of 24 notes
adg5408/adg5409 data sheet rev. b | p age 24 of 24 notes ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09206 - 0- 5/12(b)

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